# Von Neumann & Harvard Architecture ## What is Computer Architecture? - Computer architecture defines how a system organizes and utilizes its components and instructions to operate - It's essentially the blueprint of how the computer's hardware works together - Two primary architecture models exist: - **Von Neumann architecture** - **Harvard architecture**

Computer architecture describes the organizational structure and operational design of a computer system

## Comparison Overview | Architecture | Memory Organisation | Bus | Address Space | Control Units | Usage | |--------------|---------------------|-----|---------------|---------------|-------| | Von Neumann | Unified Memory | Single | Shared | Single Control Unit | Most modern computers, microcontrollers | | Harvard | Separated Memory | Separate | Distinct | Separate Control Units | Specialized embedded systems | ## Von Neumann Architecture ### Key Characteristics - Uses a **single, unified memory** space for both instructions and data - Both program code and data values are stored in the same memory location - Single set of buses connects CPU to memory - Data and instructions share the same pathways

Think of Von Neumann like a single-lane road where cars (data) and buses (instructions) must share the same route

### Components #### Control Unit (CU) - Manages and coordinates processor operations - Retrieves instructions from memory - Decodes/interprets instructions - Executes instructions - Generates timing signals to synchronize all computer activities #### Arithmetic Logic Unit (ALU) - Performs all mathematical operations: - Addition - Subtraction - Multiplication - Division - Executes logical operations: - Comparisons - Boolean logic (AND, OR, NOT, etc.) #### Special Registers - Small, fast storage locations inside the CPU - Each register has a specific purpose - Faster access than RAM #### Single Bus System - Connects CPU to memory and I/O devices - Three types of buses work together: - **Data bus**: Carries actual data - **Address bus**: Carries memory location addresses - **Control bus**: Carries control signals for coordination #### Memory (RAM) - Stores both data and instructions in identical format - Memory is divided into addressable cells - Forms a linear/sequential array of bytes - Each cell can be accessed by its unique address

Von Neumann bottleneck occurs when the single bus limits data transfer rate between CPU and memory

## Harvard Architecture ### Key Characteristics - Uses **physically separate memory** for instructions and data - Instruction memory and data memory are completely independent - Separate buses for instruction fetches and data transfers - No competition between instruction fetches and data access

Harvard is like having two parallel roads: one exclusively for data traffic, another exclusively for instruction traffic

### Components #### Separate Instruction and Data Memory - System maintains distinct memory units - One memory unit dedicated to program instructions - Another memory unit dedicated to data values - Enables simultaneous access to both instructions and data - Greater speed and efficiency as operations don't interfere with each other #### Separate Instruction and Data Buses - Independent bus systems prevent interference - Instruction bus handles only instruction fetches - Data bus handles only data transfers - Data operations don't slow down instruction fetching - Results in improved overall system performance #### Control Unit (CU) - Controls processor and component operations - Retrieves instructions from instruction memory - Decodes and interprets instructions - Executes instructions - Generates timing signals - Manages all computer system units #### Arithmetic Logic Unit (ALU) - Performs all arithmetic calculations: - Addition - Subtraction - Multiplication - Division - Executes logical operations: - Comparisons - Boolean operations (AND, OR, NOT, XOR, etc.) ## Harvard Performance Advantages Over Von Neumann ### Architectural Improvements | Feature | Explanation | |---------|-------------| | Two separate areas of memory | One for instructions and one for data
Instructions and data can be accessed concurrently | | Different sets of buses | One for instructions and one for data
Instructions and data can be accessed concurrently | | Pipelining | Whilst an instruction is being executed the next can be decoded and the subsequent one fetched | | Use of Cache | A small amount of high performance memory which is next to the CPU
It stores frequently used data and instructions | | Virtual cores / Hyperthreading | This is where a physical core can act as two virtual cores | | Multiple Cores | Each core acts as a separate processing unit | | Onboard Graphics | Built-in circuitry for graphics processing | | Performance boosting mode | The clock speed can be temporarily increased for a performance boost | | Out of Order Execution | Instructions can be executed before earlier ones if they are ready | | Super Scalar | Multiple instructions can be executed simultaneously | ### Concurrent Access - Harvard architecture's main advantage is **parallel operation** - While the CPU reads an instruction from instruction memory, it can simultaneously read data from data memory - Example: Imagine a chef (CPU) who can look at a recipe (instruction) while simultaneously grabbing ingredients (data) - much faster than having to put down the recipe every time they need an ingredient ### Reduced Bottlenecks - No single bus congestion - Instruction fetches don't compete with data transfers - Think of it like a kitchen with two doors: one for servers bringing orders in, another for servers taking food out - no collisions in the doorway ### Enhanced Throughput - Multiple operations occur in parallel - System can maintain higher instruction processing rates - Like having separate checkout lanes for customers with baskets versus trolleys - both move faster ## Contemporary Processor Architecture - Modern processors don't strictly follow pure Von Neumann architecture - Most implement **hybrid approaches** combining features from both architectures - Contemporary processors include advanced features: - Cache memory hierarchies (L1, L2, L3) - Multiple processing cores - Instruction and data caches (Harvard-like separation at cache level) - Out-of-order execution capabilities - Superscalar execution (multiple instructions per clock cycle) - Hyperthreading/simultaneous multithreading

Contemporary processors use Von Neumann architecture at the main memory level but implement Harvard principles in cache organization

### Example: Modern Desktop CPU - Uses unified main memory (Von Neumann approach) - Implements separate L1 instruction and data caches (Harvard approach) - Shares L2 and L3 caches for both instructions and data - Best of both worlds: flexibility of Von Neumann with speed benefits of Harvard

Questions about contemporary architecture require awareness of how modern processors differ from pure Von Neumann design

## Key Differences Summary ### Von Neumann - **Memory**: Single unified memory for instructions and data - **Buses**: Single set shared between instructions and data - **Complexity**: Simpler design, easier to implement - **Cost**: More economical - **Speed**: Potential bottleneck due to shared bus - **Use case**: General-purpose computing, standard PCs, laptops ### Harvard - **Memory**: Separate physical memory for instructions and data - **Buses**: Separate buses for instructions and data - **Complexity**: More complex design - **Cost**: More expensive due to additional hardware - **Speed**: Faster due to parallel access - **Use case**: Real-time systems, digital signal processors, embedded systems ## Practical Applications ### Von Neumann Usage - Desktop computers - Laptop computers - Smartphones (modified implementation) - General-purpose servers - Gaming consoles (with modifications) ### Harvard Usage - Microcontrollers in appliances (washing machines, microwaves) - Automotive engine control units - Digital signal processors in audio equipment - Industrial control systems - Medical device embedded systems

Choose Harvard when speed and real-time processing are critical; choose Von Neumann for flexibility and lower cost

## Architecture Selection Considerations ### When to use Von Neumann: - General-purpose computing needs - Cost is a significant factor - Program flexibility is required - Self-modifying code might be needed - Standard software development environment ### When to use Harvard: - Real-time processing requirements - Predictable, consistent performance needed - Safety-critical applications - Digital signal processing tasks - Embedded systems with fixed functionality ## Memory Organisation Impact ### Von Neumann Memory Model - Instructions like `LOAD 150` and `STORE 150` access the same memory space - Memory address `150` could contain either an instruction or data - Simpler memory controller required - More flexible but potential for conflicts ### Harvard Memory Model - Instruction address `150` and data address `150` refer to different physical locations - No possibility of instruction/data conflicts - Requires more complex memory management - More reliable for safety-critical systems

Address space refers to the range of memory addresses that can be accessed by the processor